The invention relates to the field of tools and methods for integrated circuit design. In particular the invention relates to tools and methods for generating a library of cells for use on mask-programmed gate array integrated circuit designs.
Integrated circuits require a sequence of masking steps during fabrication, these masking steps are interspersed with a variety of oxide growth, etching, ion implanting, deposition, and other processing steps. Each masking step typically requires use of a costly mask and defines a single layer of the many layers of the resulting integrated circuit.
Mask-programmed gate array integrated circuits are manufactured with a sequence of masks. They use a regular pattern of low-level structures so that low-level masks may be common to several integrated circuit types, but use higher-level masks custom tailored to each type of circuit manufactured. With this technique, fewer custom masks need be manufactured for each type of circuit than with full-custom designs. It is also possible to stockpile partially-manufactured integrated circuits so that first prototypes of new integrated circuit types can be produced more quickly than with fully customized mask sets. The partially manufactured circuit as defined by the low-level masks can be described as a base array.
A typical CMOS gate array has a large number of low-level cells, each low-level or transistor cell containing a fixed pattern of transistors of P and N channel types. These cells are produced by the common low-level masks, some of the transistors of these cells are interconnected by customized higher-level interconnect produced by the higher-level customized masks to form the desired circuit.
In designing a digital integrated circuit, most engineers do not design at the transistor level. Most engineers design circuits comprising a hierarchy of logical cells interconnected to perform a desired function. Typical logical cells include RS, D or JK flip-flops, latches, inverters, and adders, as well as NAND, NOR, XOR, OR, and AND gates. These logical cells are often selected from a cell library for placement into the design.
Cells of a logical cell library are often characterized for speed so that they may be modeled at the gate level. Simulations of the circuits may then be performed at gate level for verification of the integrated circuit design.
It is known that a logical cell library may be constructed such that each cell of the library is built from gate array transistor cells with logical-cell internal interconnect. The logical-cell internal interconnect connects transistors of the transistor cells into a circuit for performing the function of the logical cell. These cells may then be placed and connected to form the logic of the integrated circuit. For example, a logical cell library built on gate-array transistor cells of peculiar form is described in U.S. Pat. No. 6,031,982. The libraries of logical cells provided by different manufacturers, or even by a single manufacturer for different processes, often contain different logical cell types.
Once the cell library is built, a netlist is generated for the integrated circuit. This netlist is generated through synthesis or extraction of a schematic as known in the art. The netlist indicates the logical cells required for the integrated circuit and their interconnections.
Logical cells are placed in the layout of the integrated circuit such that they align with the transistor cells of the gate array. Placement may be by hand or may be accomplished by automatic placement software as known in the art. Next, the interconnect specified by the netlist is generated and inserted into the layout; this interconnect may be generated by hand or by routing software as known in the art. Once the interconnect is generated, the logical cell""s parasitic resistance and capacitance parameters may be extracted for final verification. Masks are then made for the upper levels of the integrated circuit and used to transform base arrays into completed integrated circuits.
Masks used for manufacture of integrated circuits are subject to design rules that vary with the process on which the circuits are to be made. Processes vary from manufacturer to manufacturer as well as with the level of technology. These rules specify minimum dimensions for shapes as well as minimum spaces between shapes. They also specify relationships between shapes defined by different masks. For example, a design rule may require that a contact be overlapped by metal of a specified width.
The base array of a gate-array design also imposes constraints on the higher-level interconnect. For example, connections to the transistors can only be made at particular locations in each transistor-level cell; these locations may change if the cell is modified to fit design rules for a different process. Similarly, these locations may change if the cell is modified for other reasons such as to improve its radiation hardness or latchup resistance.
Construction of a base array is typically done by manual layout. Construction of a library of logical cells for a specific process is typically done by manual layout of logical-cell internal interconnect. These time-consuming tasks must be repeated for each base array design and process on which the library is to be supported. New processes and base array designs are being introduced, and design rules for others refined, at an increasingly rapid pace, making such manual construction expensive.
It is desirable to have a way to quickly and automatically generate a logical cell library and base array for each process to be used. This cell library should have a standardized selection of logical gates, flip-flops, and other cells so that circuit designs initially created for one process and base array combination can be quickly converted for manufacture on another process and base array. This is particularly important to foundry-independent semiconductor companies such as Aeroflex UTMC because of the need to quickly map designs for manufacture at different wafer fabrication plants.
Cadence Design Systems, Inc. (Cadence) is a supplier of computer-aided design software to the integrated circuit design industry. Many Cadence layout tools support the SKILL language for automating manual tasks and customizing the software.
A technology file is a way of representing information including the design rules of a particular process in machine-readable form such that these rules may be used by design software tools. Cadence tools support a machine-readable technology file having a physical rules class. The physical rules class permits definition of spacing rules for the following:
width of objects on a particular layer (minWidth)
the minimum space of a notch in an object on a particular layer (minNotch)
the minimum distance allowed between objects (minSpacing)
the amount of space required when one object encloses another (minEnclosure)
Relative Object Design (ROD) is a SKILL language procedural interface provided by Cadence which allows a programmer to:
Assign names to geometrical objects, including rectangle instances and paths;
Access objects and points through all levels of hierarchy,
Align ROD objects to each other or to specific coordinates;
Create user-defined handles for aligning of objects including interconnect; and
Use of a technology file to enforce spacing, width, enclosure, and overlap rules.
ROD function parameters may be set by the technology file, or can be written directly by the designer in SKILL code. These function parameters can also be set to an arithmetic combination of technology file and other parameters.
Cadence promotes use of ROD-based transistor-level parameterized cells (PCELLS) with their integrated circuit layout editors. These PCELLS are known to support generation of layout for CMOS single and multiple-gate transistors, snaked resistors, capacitors, guard rings, shielded wires, and similar component structures for use within cell layouts such as used in full-custom integrated circuit designs. These components are not logical cells, but may be used within logical cells.
ROD-based PCELLS used with Cadence""s Virtuoso layout editor permit insertion into a custom layout of a transistor cell that meets all minimum design rules and has a gate, source, and drain with source and drain contacts. Device sizing and layout may then be altered by changing parameters either directly or by stretching the cell with the editor. The PCELLS can automatically produce multiple gate legs and merge the source and drain regions of adjacent transistors.
Cadence""s Relative Object Design (ROD) software can define simple and complex layout objects and their interrelationships, without using low level SKILL language functions. ROD allows the user to create objects and define their relationships at more abstract levels than previously required. ROD accepts design hierarchy which simplifies the calculations required to create and align geometries.
A handle is an attribute of a ROD object. A handle can define a location for future alignment, or a specific characteristic of the object. The system automatically defines a number of handles for a ROD object:
Bounding box point handles
at each corner (uL uR lL lR)
in the center of each edge (uC cL cR lC)
in the center of the bounding box (cC)
bounding box width and length parameter handles segment point handles
at the beginning, middle and end of each segment. (startn, midn, and endn, where n is the segment number)
for paths, two additional point handles:
startCenter0 and endCenterLast
segment length parameter handles
Handles may also be defined by a programmer using the ROD system. These xe2x80x9cuser-definedxe2x80x9d handles may be assigned to specific locations within a ROD object such as a block or a cell. Handles can be accessed from higher levels of a hierarchical design.
Documentation on the ROD system, the Virtuoso layout editor, Cadence PCELLS, and SKILL is available from Cadence Design Systems, Inc., 2655 Seely Road, San Jose, Calif. 95134 (408) 943-1234.
Aeroflex UTMC has developed a methodology to use Cadence""s Relative Object Design (ROD) software in conjunction with the regularity of our gate array architecture to define an entire logical cell library in terms of aligned ROD objects and internal routing.
A technology file is prepared that describes the design rules of a target process in machine-readable form. This may be done as a Cadence Design Framework II technology file.
The regular pattern of n-channel and p-channel devices of the gate array architecture is described as a transistor-level cell with ROD alignments.
Hierarchy is employed to reduce the amount of SKILL code required. A small set of common building blocks are sufficient to create the entire library. For example, a two-input AND (AND2) logical cell is composed of NAND and Inverter building blocks. The AND2 cell comprises the alignment of the Inverter and NAND building block instances and any required interconnect between them. Internal cell routing is simplified with the creation of programmer-defined ROD handles.
Other cell types are built similarly to the AND2 cell, some but not all of these additional cell types also utilize the NAND and Inverter building blocks heretofore described.
A SKILL Makefile invokes all ROD SKILL code in a certain sequence, and generates the entire library. A postprocessing step then modifies the layouts of the cells of the library to satisfy electromigration rules. A parameter extraction step may then be run to derive model parameters for characterization. Characterized models are used for design verification of circuits built using the library.
Whenever it is necessary to generate a logical cell library for a second process with different design rules, a copy of the technology file is prepared that describes the design rules of the second process. The Makefile and postprocessing steps are reinvoked to produce layouts of the cells of the cell library that are tailored to the second process. This generated library may then be extracted and characterized to derive characterized models for design verification.